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STRUCTURE NAME OF PRODUCT TYPE FUNCTION
Silicon Monolithic Integrated Circuit DC-AC Inverter Control IC
2ch control with Push-Pull Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Circuit protection with Timer Latch Under Voltage Lock Out Over Voltage Protection Mode-selectable the operating or stand-by mode by stand-by pin BURST mode controlled by PWM and DC input Output linear Controllable Analog dimming by external DC voltage Synchronous operating the other several BD9896FV IC's
Absolute Maximum RatingsTa = 25
Parameter Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation Maximum Junction Temperature
*
Symbol VCC Topr Tstg Pd Tjmax
Limits 15 -40+90 -55+150 1062* +150
Unit V mW
Pd derated at 8.5mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Recommended operating condition
Parameter Supply voltage Output oscillation frequency BCT oscillation frequency Symbol VCC fout fBCT Limits 6.014.0 2590 0.051.00 Unit V kHz kHz
Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority.
REV. C
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Electric CharacteristicsTa=25VCC=7V
Parameter WHOLE DEVICE Operating current Stand-by current OVER VOLTAGE DETECT FB over voltage detect voltage STAND BY CONTROL Stand-by voltage L Input voltage range of Slave setting Input voltage range of Master setting TIMER LATCH Timer Latch voltage Timer Latch current BURST MODE BOSC Max voltage BOSC Min Voltage BOSC constant current BOSC frequency OSC BLOCK MAX DUTY Soft start current IS COMP detect Voltage SS COMP detect voltage SRT ON resistance UVLO BLOCK Detect voltage (VCC_UVLO) Hysteresis width (VCC_UVLO) Operating voltage (UVLO) Hysteresis width (UVLO) REG BLOCK REG output voltage REG source current FEED BACK BLOCK IS threshold voltage IS threshold voltage VS threshold voltage IS source current 1 IS source current 2 VS source current VREF input voltage range OUTPUT BLOCK NB output voltage NA output voltage NB output voltage L NA output voltage L NB output sink resistance NB output source resistance NA output sink resistance NA output source resistance Drive output frequency COMP BLOCK Overr voltage detect Hysteresis width (COMP) PROTECT CLOCK FAIL-pin On resistor value R_FAIL 200 400 SYNCRO BLOCK CT_SYNC_IN_High input Voltage Range VCT_SYNC_IN_H 2.0 VCC*0.8 CT_SYNC_IN_Low input Voltage Range VCT_SYNC_IN_L -0.3 1.5 CT_SYNC_IN Pull-up resistor RCT_SYNC_IN_pull_up 500 VCT_SYNC_IN CT_SYNC_IN Self-oscillation voltage VCC0.9 VCC RCT_SYNC_OUTsink CT_SYNC_OUT sink resistor value 150 300 RCT_SYNC_OUTsource CT_SYNC_OUT source resistor value 370 740 CT_SYNC_OUT_High output Voltage Range VCT_SYNC_OUT _H 2.8 3.1 3.4 CT_SYNC_OUT_Low output Voltage Range VCT_SYNC_OUT_L 0.5 SRT SYNC Exchange detect Voltage Vsrtc 0.5 0.8 1.1 This product is not designed for normal operation with in a radio active environment. V V k V V V V Symbol Icc1 Icc2 Vovf VstL VstH1 VstH2 Vcp Icp VburH VburL IBCT fBCT MAXDUTY Iss Visc Vssc RSRT Vcc_vuvlo Vcc_vuvlo Vuvlo Vuvlo VREG IREG Vis Vis Vvs Iis1 Iis2 Ivs VREF IN VoutNBH VoutNAH VoutNBL VoutNAL RsinkNB RsourceNB RsinkNA RsourceNA fOUT VCOMPH VCOMPH MIN. 2.20 -0.3 1.8 2.55 1.9 0.5 1.94 0.4 1.35/BRT 292.5 44 1.0 0.45 2.0 5.100 0.150 2.260 0.075 3.038 5.0 1.225 1.220 13.0 0.6 VCC-0.3 VCC-0.3 57.9 2.4 0.040 Limits TYP. 2.40 2.0 1.0 2.0 0.5 1.5/BRT 300 46.5 2.0 0.50 2.2 200 5.300 0.200 2.340 0.100 3.100 1.250 VREFIN 1.250 20.0 VCC-0.1 VCC-0.1 0.1 0.1 5 8 5 8 60.0 2.5 0.060 MAX. 17.0 10 2.60 0.8 2.25 VCC 2.1 1.5 2.06 0.6 1.65/BRT 307.5 49 3.0 0.55 2.4 400 5.500 0.250 2.420 0.125 3.162 1.275 VIS 1.280 1.5 27.0 1.0 1.6 0.3 0.3 10 16 10 16 62.1 2.6 0.080 Unit mA A V V V V V A V V A Hz % A V V V V V V V mA V V V A A A V V V V V KHz V V
VREF pin:OPEN,REG is shorted VREF pin is supplied
Conditions CT_SYNC_IN=Low CT_SYNC_IN=OPEN
fBCT=0.3kHz fBCT=0.3kHz BRT=36k BCT=0.048F fout=60kHz
DUTY=2.2V DUTY=0VIS=0.5V Over 1.25V effective is not
Isink = 10mA Isource = 10mA Isink = 10mA Isource = 10mA RT=15.94k
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Package Dimensions
Device Mark
BD9896FV
Lot No.
SSOP-B28 (Unit:mm)
Block Diagram
VCC REG CT_SYNC_IN CT_SYNC_OUT RT BRT BCT DUTY
Pin Description
REG Block SYSTEMON/OFF STB STB Block Master/Slave
OSC
BOSC
DUTY Block
1 2
NA1 NB1 CP REG FAIL VREF
CT_SYNC_OUT CT_SYNC_IN
FET driver for 1ch
CT UVLO Block VCC UVLO
3 4
VCC
SS FB1 IS1 VS1 F/B Block PWM Block LOGIC Block
FET driver for 1ch External capacitor from CP to GND for Timer Latch Internal regulator output Protect clock output Reference voltage Output pin of CT synchronous signal Input pin of CT synchronous signal External resistor from SRT to RT for adjusting the triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator GROUND External capacitor from BCT to GND for adjusting the BURST triangle oscillator External resistor from BRT to GND for adjusting the BURST triangle oscillator Control PWM mode and BURST mode Stand-by switch, Master/Slave selection Error amplifier input Error amplifier input Error amplifier output Error amplifier input Error amplifier input Error amplifier output External capacitor from SS to GND for Soft Start Control Over voltage detector Supply voltage input External Under Voltage Lock OUT FET driver for 2ch FET driver for 2ch Ground for FET drivers
5
NA1 NB1
SS CT
OUTPUT Block
6 7 8
FB2 IS2 VS2 VREF F/B Block PWM Block LOGIC Block
VCC SS CT OUTPUT Block NA2 NB2
9 10
RT SRT GND BCT BRT DUTY STB VS2 IS2 FB2 VS1 IS1 FB1 SS COMP VCC UVLO NB2 NA2 PGND
PGND GND PROTECT Block FAIL
11 12
SRT
COMP
CP
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
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NOTE FOR USE
When designing the external circuit, including adequate margins for variation between external devices and the IC.Use adequate margins for steady state and transient characteristics. Recommended Operating Range The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however, the variation will be small. Mounting Failures Mounting failures, such as misdirection or miscounts, may harm the device. Electromagnetic Fields A strong electromagnetic field may cause the IC to malfunction. . The GND pin should be the location within 0.3V compared with the PGND pin
BD9896FV has the short circuit protection with Thermal Shut Down System. When STB or Vcc pin re-supplied, They enables to cancel the latch. If It rise the temperature of the chip more than 170(TYP), It make the external FET OFF Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch. By STB voltage, BD9896FV is changed to 3 states. Therefore, do not input STB pin voltage between one state and the other state (0.81.8, 2.252.55). The pin connected a connector need to connect to the resistor for electrical surge destruction. This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, (When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) (When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND(P substrate)voltage to an input pin.
(PinA) Resistance (PinB) C Transistor (NPN) B E GND P P N P substrate GND Parasitic diode N P P substrate GND Parasitic diode (PinB) (PinA) B Parasitic diode GND
N
N
C E GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. C
Notice
Notes
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